The present invention relates to semiconductor memory devices, and in particular dynamic random access memory (DRAM) devices.
In a semiconductor memory device, such as a dynamic random access memory (DRAM) device, a sense amplifier is provided to sense a small potential difference between a reference voltage and voltage on an active bitline pair connected to a memory storage cell in a memory array segment. The sense amplifier amplifies the small difference from which a binary state is determined for the memory storage cell.
In a typical DRAM, the sense amplifier is shared by first and second memory array segments to sense voltage on bitlines to either one memory array segment or the other memory array segment, but never sensing from both memory array segments at the same time. To this end, a first multiplexer is provided that connects a sense node pair of the sense amplifier to, and disconnects the sense node pair from, the first memory array segment. A second multiplexer is provided that connects the sense node pair of the sense amplifier to, and disconnects the sense node pair from, the second memory array segment. Control logic is provided in the memory device to generate multiplexer control signals that control the state of the first and second multiplexers depending on the state of selection signals. The selection signals are derived from control and address signals in order to select the appropriate memory array segments for access.
Certain DRAM devices, such as those targeted for low power consumption applications necessarily have aggressive current specification targets. One known technique to meet these specifications is to force a multiplexer to disconnect a sense amplifier from a memory array having a bitline leakage anomaly when the memory array is unselected. This programmable off-state control prevents wordline-bitline short-circuit current from flowing through the sense amplifier. However, it can also increase operating current of the multiplexer lines by preventing multiplexer lines from being precharged from power supplies before transitioning to a pumped higher voltage level, thus requiring more current from pump source to precharge the sense nodes.
Another power consumption conservation technique is to reduce self-refresh current in a DRAM device by latching the multiplexer state upon activation by a control signal. The multiplexer remains latched in a particular state (and thus cannot be switched to another state) until another control signal activation changes its state. The benefit of this non-dynamic latching technique is that it reduces multiplexer switching current by eliminating the need to reset the multiplexer to a default state. However, the drawback of this technique is that the multiplexer state cannot be programmed to block wordline-to-bitline short-circuit current. Latched states in memory arrays are non-deterministic and result from random address patterns. Sensitivities that arise from different latched state combinations in a memory array cannot be screened-out during manufacturing because the number of state combinations is too large for efficient testing.
What is needed is a control circuit arrangement that combines a programmable off or disconnected state for a multiplexer together with a dynamic latching mode that operates when a memory array segment of a DRAM device is consecutively accessed multiple times for any of a variety of reasons, such as self-refreshing a memory array.